1. Field of the Invention
The present invention relates to a plasma display, and more particularly, to a plasma display panel driver and a driving method thereof.
2. Description of the Related Art
Plasma display panels (PDPs) have recently been popularized from among flat panel displays because of their high brightness and light emission efficiency, and wider view angles.
A PDP is a flat display for showing characters or images using plasma generated by gas discharge. PDPs can include pixels numbering more than several million in a matrix format, in which the number of pixels are determined by the size of the PDP. A PDP structure will now be described.
Along with the general structure of the PDP, an electrode arrangement of the PDP will also be described.
The PDP includes glass substrates 1 and 6 facing each other with a predetermined gap therebetween. Scan electrodes and sustain electrodes in pairs are formed in parallel on the glass substrate, and the scan electrodes and the sustain electrodes are covered with a dielectric layer and a protection film. A plurality of address electrodes is formed on the glass substrate, and the address electrodes are covered with an insulator layer. Barrier ribs are formed on the insulator layer between the address electrodes, and phosphors are formed on the surface of the insulator layer and between the barrier ribs. The glass substrates are provided facing each other with discharge spaces between the glass substrates so that the scan electrodes and the sustain electrodes can cross the address electrodes. A discharge space between an address electrode and a crossing part of a pair of a scan electrode and a sustain electrode forms a discharge cell, which is schematically indicated.
The electrodes of the PDP have an (n×m) matrix structure in which a plurality of address electrodes are arranged in the vertical direction and a plurality of scan electrodes and sustain electrodes are arranged in pairs in the horizontal direction.
In general, a frame is divided into a plurality of subfields in the PDP, and gray scales are represented by combinations of the subfields. Each subfield has a reset period, an address period, and a sustain period. In the reset period, wall charges formed by a previous sustain discharge are erased, and wall charges are set up in order to perform a stable next address discharge. In the address period, cells which are turned on and cells which are not turned on are selected, and the wall charges are accumulated on the turned-on cells (addressed cells). In the sustain period, a sustain discharge for actually displaying images on the addressed cells is performed.
A conventional PDP driving waveform diagram, and a state of a wall voltage and an applied voltage caused by a PDP driving waveform is described as follows. The reset period will only be described in the PDP driving waveform.
The reset period includes an erase period, a rising ramp period, and a falling ramp period.
In the erase period, a voltage waveform which rises to a voltage of Ve from a reference voltage is applied to the sustain electrode while the scan electrode is maintained at the reference voltage after a sustain period of a previous subfield is finished, and accordingly, positive wall charges and negative wall charges respectively formed on the sustain electrode and the scan electrode are erased after the last sustain discharge of the previous subfield is finished.
In the rising ramp period, a ramp voltage which gradually rises to a voltage of Vset which is greater than a firing voltage from a voltage of Vs which is less than the firing voltage is applied to the scan electrode. While the ramp voltage rises, weak discharges are respectively generated to the address electrode and the sustain electrode X from the scan electrode Y. Negative wall charges are stored in the scan electrode and positive wall charges are stored in the sustain electrode by the weak discharges.
In the falling ramp period, a ramp voltage which gradually falls to a negative voltage of from the voltage of is applied to the scan electrode. While the ramp voltage falls, weak discharges are generated to the scan electrode from the sustain electrode and the address electrode by the wall voltage formed at the discharge cells. Part of the wall charges formed on the sustain electrode, the scan electrode, and the address electrodes are erased by the weak discharges thereby reaching a state suitable for addressing.
In general, when the wall voltage of Vw between the scan electrode and the sustain electrode at the last point of the rising ramp period is defined to be Vw0, the discharge is started when the difference between the voltage of Vw0 and an applied voltage Vin (the voltage difference between the scan electrode and the sustain electrode) exceeds the firing voltage of Vf.
No discharge is generated in the earlier stage ‘a’ of the falling ramp period since the voltage difference between the voltage of Vw0 and the applied voltage is less than the firing voltage Vf. Therefore, the conventional driving waveform problematically increases the reset time because of an unnecessary reset operation such as the initial period of ‘a’ in the falling ramp period.